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ZW50F15AD1_Datasheet PDF

发帖时间:2021-06-15 02:29:49

Demand for engineers is outstripping supply. Many companies find that their largest challenge to successful project completion is building a team with adequate resources. With the difficulty of keeping internal resources current and knowledgeable in the latest generation of microprocessors, operating systems, and protocol stacks, finding and managing external engineering expertise and capacity has become even more crucial.

TI's TMS320C64x DSP, first announced in February and expected to begin sampling by the end of the year, will have a two-level cache memory, a 32-channel enhanced direct memory access (EDMA) controller, and multiple external buses to support high-speed connections to external memories, peripherals, and host processors.

The first device in the family, the TMS320C6401, is expected to debut with performance around 700 MHz, with production scheduled for midyear 2001. TI plans to scale the family to 1.1-GHz performance.

ZW50F15AD1_Datasheet PDF

The 'C64x memory and peripheral system provides peak system performance for the world's fastest DSPs,” said Henry Wiechman, TMS320C6000 marketing manager for TI, speaking from the Embedded Processor Forum in San Jose.

Developers who move to this generation will be ahead of the curve as TI introduces code-compatible DSPs that scale to achieve more than twice today's performance with a variety of different memory and peripheral configurations to meet the needs of a broad range of applications,” he said.

The two-level cache will have 16 Kbytes of memory in each, four times the cache memory available in TI's existing TMS320C6211 DSP.

ZW50F15AD1_Datasheet PDF

The EDMA controller will be capable of transferring more than 2.6 Gbytes/s of sustained bandwidth. With a total of 85 linkable parameter sets, and four independent priority transfer cues, the EDMA maximizes concurrency and can scale to support multiple peripherals, Wiechman said.

A 64-bit synchronous external memory interface (EMIF) combines with a 16-bit secondary EMIF for external peripherals and a 32-bit host port interface (HPI) to provide more than 1.8 Gbytes of bandwidth on initial implementations of the family.

ZW50F15AD1_Datasheet PDF

Other I/O peripherals include three multi-channel buffered serial ports (McBSPs) that can compress and expand up to 128 T1/E1 channels each, as well as additional networking and video interfaces.

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Moreover, devices with 50-nm gate lengths are coming within range. Advanced Micro Devices Inc. said it fabricated a 50-nm CMOS device using a nickel-silicon-based salicide. And Intel was to present a paper suggesting that it can scale conventional planar CMOS transistors below 50 nm using conventional gate dielectric.

The nickel-silicon material used by AMD is one of the candidates to replace cobalt-silicon and titanium-silicon used to cap the gate electrodes — which are getting narrower with every process generation. AMD claims it was able to achieve a low 2 ohms/square of resistance and low junction leakage, thereby improving drive current.

Intel's Bohr said 2 ohms/square of resistance used to be common, but that contact resistance has been growing to as much as 10 ohms/square as the gate gets thinner. The move from titanium-silicon to cobalt-silicon helped reduce that resistance, but cobalt probably will have to be replaced at some point below 100 nm.

Gating factor

One possible solution presented by researchers at the University of California, Berkeley, is using a dual-metal-gate CMOS. Compared with conventional polysilicon, a dual-metal gate does more to reduce resistance and solve other problems like gate depletion and dopant penetration, the authors said.

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