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SMCJ150A R7G

发帖时间:2021-06-15 01:22:18

Now let's see how all of the concepts and parameters fit into the development of a typical modern communications transceiver. Such a communication front-end/back-end could be used to support a common US air interface like second generation (2G), narrow-band Code Division Multiple Access (CDMA) or third-generation (3G), multimedia enabled wideband CDMA (W-CDMA) systems. By changing the RF tuning, this same architecture could be used for dual”band GSM (used in Europe) or TDMA systems in the same radio band, since the processing and demodulation is performed in the post-baseband, digital section.

The advanced processor local bus (PLB) architecture maximises data transfers between the processor, crossbar and soft IP logic with high-throughput 128-bit interfaces to help minimise system bottlenecks. The auxiliary processor control Unit (APU) provides added connectivity for dedicated co-processing engines or custom user defined instructions in applications such as video processing, 3D data processing and floating-point math.

The PowerPC440 block in Virtex-5 FXT is supported by industry standard operating systems including Wind River Systems, Green Hills, and other key embedded OS providers. Linux support is provided through MontaVista, Wind River Systems with others soon to be added.

SMCJ150A R7G

To increase I/O bandwidth, the Virtex-5 FXT platform includes low-power RocketIO GTX transceivers capable of supporting data rates from 500 Mbps to 6.5Gbps. Customers can design applications supporting standards such as XAUI, Fibre Channel, SONET, Serial RapidIO, PCI Express 1.1 and 2.0, Interlaken, and others.

Consuming less than 200mW typical power per channel at 6.5Gbps, the GTX transceivers include 4-tap DFE receiver equalization in addition to linear equalization and transmit pre-emphasis to improve signal integrity at higher line rates. The transceiver blocks also include a multi-code physical coding sublayer to support both 64B/66B and 64B/67B encoding/decoding schemes saving thousands of logic cells for each channel.

The Virtex-5 FXT platform includes up to 384 DSP slices and 16.5 Mbyte of internal memory that can be configured to provide over 190 GMACs of DSP processing performance and 92 tera-bits/sec of memory bandwidth respectively at 500 MHz. Xilinx says this balance of hardware resources maximises the performance for computation-intensive applications typical of DSP and video applications. The DSP48E slice supports over 40 dynamically controlled operating modes including: multiplier, multiplier-accumulator, multipler-adder/subtractor, tree input adder, barrel shifter, wide counters and comparators.

SMCJ150A R7G

The Virtex-5 FXT FPGA platform is supported by the new ISE Design Suite 10.1 development tools which was announced March 24. This includes ISE Foundation, Embedded Development Kit (EDK), System Generator for DSP, AccelDSP synthesis tool, ChipScope Pro and ChipScope Pro serial I/O Toolkit, PlanAhead design and analysis tool and ISE simulator.

Virtex-5 FXT FPGA samples are now shipping for the FX30T and FX70T devices. The remaining FX100T, FX130T and FX200T devices will be available over the next six months with the first production devices scheduled to be made available in the third quarter of 2008.

SMCJ150A R7G

The four domain-optimised platforms – LX, LXT, SXT, and FXT – provide a range of devices that enable engineers to cost-effectively implement electronics systems by selecting an FPGA that incorporates the optimal mix of resources for their particular design: logic, I/O, and hardened IP blocks for logic-intensive, embedded processing, digital signal processing (DSP), and serial connectivity applications. Of the 24 devices in the Virtex-5 family, 15 are in full production and the rest are now sampling.

Click here for Figure 3.Figure 3: Controlled power supplies.

Stations Control: Enable/Disable Stations Similar to AP control, it is important that only the Station(s) involved in any test be the only Station(s) enabled. Automizer does exactly this in the same manner way it does with the AP tests. The Automizer determines the Station(s) involved in the test, reads the data from the Test Plan's database, and enables/disables the Station(s) accordingly.

Switch Control All APs, Chariot Console, Radius Server, and Automizer laptop/PC have Ethernet LAN connections on the same switch and on one side of the test bed. On the other side of the test bed, all Station laptops/PCs have Ethernet LAN connections on another switch and also on the other side of the test bed.

The two switches are directly connected by an Ethernet LAN cable. The second switch (on the stations side) is being controlled by Automizer through a programmable power strip to isolate the LAN segment during the wireless testing.

Software Platform The test automation platform has been developed using a combination of object-oriented language known as Visual Engineering Environment (VEE)” and Perl scripts. When combined, the two languages allow for direct control of the Chariot Test Console, which is used as the real-time monitoring probe for wireless communications between the Access Points and Stations participating in the Wi-Fi tests.

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