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发帖时间:2021-06-15 02:20:33

Custom solutions based on extended-temperature technology can be developed at Newport's design and production facilities in England.

To ensure a smooth transition with its licensing partner, MIPS Technologies, Inc. is working on an agreement to provide support to LSI Logic Corporation during this period,” said Marlon Murzello, VP of Consumer Technology Engineering at LSI Logic, Milpitas, Calif., in a statement. We are delighted that the team will be kept together and continue to function as a key driver in the development of the MIPS architecture.”

The agreement is a direct result of LSI's restructuring efforts that were announced on October 14, an LSI spokesman said. As part of an effort to cut costs, LSI has consolidated its design centers around the globe. Fiscal realities have forced us to take this step,” he said. But LSI remains strongly committed to MIPS, he said.

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Santa Clara, Calif.–Nov. 9, 1998–Chip Express Corp. (Sata Clara) now offers the conversion of existing ASIC or FPGA designs with 5V supply into its 0.35(m (3.3V/5V) CX3000 LPGA family. This service is aimed at enabling the customer to prolong product lifetime and move to an advanced technology without the need to redesign the board. Additionally, this provides the advantages of reduced production price and lower power consumption.

The ability to implement designs with 5V supply into devices operating at 3.3V is by virtue of the special Voltage Regulator (patent pending) developed by the Chip Express R&D Team. The CX3000, 0.35-(m CMOS gate array family includes the 5V Voltage Regulator and enables the smooth conversion. When 3.3V supply is not feasible, the conversion process is taking place and the Chip Express 5V Regulator is employed. In this scenario, the 5V board supply is used for the Voltage Regulator and for the design I/Os that are all operating at 5V. The supply to the core is via the Voltage Regulator and not through any power pad. The regulator converts the 5V voltage supplied from the board to a 3.3V supply for the core.

Moreover, this conversion feature is an enabling design methodology that allows using existing 5V boards while implementing new designs in a more advanced process technology, which requires 3.3V supply.

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The conversion service is available now and performed by the Chip Express Engineering Group. The cost for Design Conversion starts at $7,000 and NRE pricing starts at $20,000, dependent upon design complexity and required turnaround time. ASIC devices pricing: 140,000 available logic gates + 96,000 embedded RAM = $11.40 for 10,000 piece order; 120,000 gates + 64,000 bit RAM in 208PQFP = less than $9.00 for 100,000 units. These devices are offered with a flexible turnaround of four weeks, two weeks, one week, or one day.

Chip Express Santa Clara, CA www.chipx.com

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The contract is the first in the Cadence Services Partners Network. Steve Roddy, director of marketing for design factory strategic alliances at Cadence (San Jose, Calif.), called the network a fundamental change in the way Cadence creates service partnerships. The network is to pursue sustained, systematic relationships” as opposed to the project-based involvement more typical of design-services companies, Roddy said.

Cadence is already performing conversions of Lucent's Orca FPGAs to Lucent's family of Masked Array Conversion of Orca (Maco) devices. An automated conversion process currently targets 0.35-micron Maco devices, with an option for 0.25 micron available. The work is being done at Cadence's design center in Cary, N.C.

We're working with Cadence because their expertise and staffing will help us meet our commitments to customers without having to staff equivalent capacity in house,” said a Lucent spokesman. Cadence will perform all of the Orca-to-Maco conversions that Lucent forsees in the next couple of years, with an expected volume of around 30 per year, he said.

Customers will deal directly with Lucent, while Cadence stays in the background, Roddy said. We can interface with the customer on a technical basis if necessary, but by and large the customer will not see Cadence,” he said. Nor does it matter, he said, whether the customer uses any Cadence tools.

Cadence personnel will take in a complete FPGA programming database, timing parameters and test vectors, and create a GDSII database for the Maco ASIC in about two weeks. They will also create a Verilog model of the complete ASIC that can run on any industry-standard Verilog simulator.

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