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CD4FC561GO3F_Datasheet PDF

发帖时间:2021-06-15 02:29:02

According to Alan Yuen, director of mobile marketing at Trident, Mountain View, Calif., the CyberBlade family will save $15 to $20 over the cost of discrete components. The CyberBlade i7 is sampling now in a 492-pin BGA package for $35 in 10,000-unit lots.

In discrete form, the initial chips are expected to see use first in the embedded-control and networking markets, in devices such as high-end set-top boxes or line cards for Gbit Ethernet or ATM switches, according to IDT.

The RC32134 controller is designed to work with IDT's 32-bit processors. It is sampling now, and is expected to be ramped to volume production next month. The device will cost $19.80 in 10,000s. The RC64145 will sample in March, with volume production set for May. Designed for use with 64-bit processors, it is priced at $41 in the same volume.

CD4FC561GO3F_Datasheet PDF

SAN DIEGO — Applied Micro Circuits Corp. (AMCC) has begun marketing an off-the-shelf, CMOS quad-channel transceiver for Fibre Channel applications. The S2076 is packaged in a 208-pin TBGA package measuring 23 mm2 and priced at $65 in 100-piece quantities.

The S2076 is designed for high-speed serial data transmission over fiber-optic or copper interfaces. Each of its four channels operates at 1,062 MHz to meet the ANSI X3T11 specification. Power dissipation is 2.3 W from a 3.3-V supply, or 575 mW/channel.

Each of the four bidirectional channels performs framing for block-encoded data, in addition to parallel-to-serial and serial-to-parallel data conversion, over fiber optic, twinax, coax or TTL-compatible interfaces, the company said. Clock generation is performed by an on-chip transmit PLL that synthesizes the high-speed clock from a 106.2-MHz or 53.1-MHz reference. The on-chip quad-receive PLL synchronizes directly to the incoming data stream for clock recovery and data retiming.

CD4FC561GO3F_Datasheet PDF

Call (800) 755-AMCC, ext. 2622www.amcc.comEETInfo No. 609

Analog Devices Inc. last week bolstered its position in the increasingly competitive DSP market by agreeing to acquire two DSP-tool-development companies for $20 million in cash and stock.

CD4FC561GO3F_Datasheet PDF

The investments were seen as possible pre-emptive strikes against DSP market leader Texas Instruments Inc., which made several similar acquisitions in the past two years.

Tools are becoming increasingly important, perhaps even more important than processor architectures themselves,” said Jeff Bier, general manager of Berkeley Design Technology Inc., based in Berkeley, Calif.

Although it could continue assigning computing tasks to its workhorse C6xx DSP, TI's integrated dual-processor approach offers customers' the ability to partition their functions between both a DSP and MCU core, Strauss said. Motorola Inc., for example, already has combined its own DSP and a PowerPC core for use in its QICC networking products, he added.

In addition, MIPS, like ARM, commands a sizable base of software and peripheral designers that enjoy working with the architecture, Kerslake said. The MIPS architecture received renewed support last month when Toshiba Corp. and NEC Corp. signed separate 10-year commitments to continue using the technology.

Both MIPS and ARM have a very high following, with support from several operating systems and software for development,” said Max Baron, micro logic analyst for Scottsdale, Ariz.-based In-Stat Inc. In total, MIPS claims more than 150 separate tool software applications have been designed for its cores.

What gives MIPS the edge in some applications, Baron said, is the fact that it counts communications IC maker Broadcom Corp. among its roster of licensees. Broadcom's interest could well have been interpreted by TI as a sign that the core will be designed into a high-volume communications architecture, Baron said.

Outlining specific plans, TI said it will fabricate the 32-bit Jade synthesizable core on a 0.18-micron process this quarter. The chip should run at 150 MHz, producing about 150 to 170 Dhrystone MIPS. Occupying about 10 sq. mm, the device will integrate 8 Kbytes each of instruction and data cache and a memory management unit. No performance targets were given for the 64-bit Opal core, although the die size at 0.15-micron linewidths is also expected to be about 10 sq. mm, Kerslake said.

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